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File:CMOS NAND Layout.svg

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Summary

Description
English: The physical layout of a CMOS NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup.
עברית: שער לוגי מסוג NAND ממבט על.
Polski: budowa bramki NAND CMOS.
Română: Aranjamentul fizic al unei porţi NAND CMOS.
中文:CMOS与非门的布图.
CMOS NAND Layout for chip
Date 7 September 2006 (original upload date)
Source Transferred from en.wikipedia to Commons.
Author Jamesm76 at English Wikipedia
Other versions Derivative works of this file:  CMOS AND Silicon.svg

Licensing

Public domain This work has been released into the public domain by its author, Jamesm76 at English Wikipedia. This applies worldwide.
In some countries this may not be legally possible; if so:
Jamesm76 grants anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

Original upload log

The original description page was here. All following user names refer to en.wikipedia.
  • 2006-09-07 23:46 Jamesm76 294×587×0 (11839 bytes) I am the author and I release this to the public domain.
  • 2006-09-07 23:27 Jamesm76 294×587×0 (11827 bytes) SVG drawing of a CMOS NAND gate replacing the older PNG version I had previously uploaded ("CMOS NAND Layout.png"). I am the author and I release this to the public domain.

Captions

Schematic of CMOS NAND circuit layout

Items portrayed in this file

depicts

image/svg+xml

8ea0af40053d6a41831555d95303d3062b643ade

11,839 byte

587 pixel

294 pixel

File history

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Date/TimeThumbnailDimensionsUserComment
current20:46, 19 October 2007Thumbnail for version as of 20:46, 19 October 2007294 × 587 (12 KB)Prolineserver{{Information |Description=''no original description'' |Source=Originally from [http://en.wikipedia.org en.wikipedia]; description page is/was [http://en.wikipedia.org/w/index.php?title=Image%3ACMOS_NAND_Layout.svg here]. |Date=2006-09-07 (first version);

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